Kaby lake – microarchitectures – intel – wikichip electricity human body

Kaby Lake is set to be released in two phases. The first phase was announced in August of 2016 and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by Kaby Lake Y and Kaby Lake U CPUs. Intel released mainstream Kaby Lake S and Kaby Lake H processors on January 3, 2017 in time for CES 2017. The enthusiast version, Kaby Lake X, was introduced during Computex Taipei 2017.

Kaby Lake uses a modified and improved 14 nm process used for the Broadwell microarchitecture (And Skylake). Intel calls the modified process "14nm+". The new process has improved transistor channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 megahertz which gives many single-thread applications a modest performance increase. Overall transistors improvement allowed for +12% drive current.

While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly overclockable with models such as the Core i7-7700K capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup.

Kaby Lake builds upon the Skylake architecture, most dies are slight enchantments of their Skylake counterparts. The biggest change is the removal of the high performance quad core GT4 die, which has been replaced by the Kaby Lake G processors. And the introduction of the first low power quad core processor.

Support for three displays via HDMI 1.4 [graphics 1], DisplayPort (DP) 1.2, and Embedded DisplayPort (eDP) 1.4 interfaces. Kaby Lake’s biggest enhancement is the addition of native fixed function HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as fixed function HEVC/VP9 encoding for 4K (8-bit).

• ↑ Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an LSPCON ( Level Shifter/ Protocol Converter) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.

Kaby Lake Y and U are single-chip solutions. Y chips utilize a 2-die multi-chip package (MCP) whereas the Kaby Lake U’s are either 2 or 3-die MCP configuration. The 3 die chip configuration are for the Iris IGPs which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. Kaby Lake S and H are a two-chip solution linked together via Intel’s standard DMI 3.0 bus interface which utilizes 4 of the CPU’s 20 PCIe 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only Kaby Lake S (used on mainstream desktop processors) are not soldered onto the motherboard and can be interchanged/replaced.

All parts incorporate 4 GiB of HBM 2 along with an AMD Vega GPU. The HBM2 and GPU are interconnected using Intel’s EMIB, however, the CPU and GPU are connected using standard in-package wires over standard PCIe 3.0. x8 lanes are permanently reserved for direct GPU-CPU communication. This leaves x8 additional lanes for all other peripherals that need direct connection to the CPU.

Intel claims that the use of HBM2 instead of GDDR5 results in 80% less power. It’s worth noting that since those are Kaby Lake H parts with Radeon Graphics, they effectively have two GPUs and both GPUs are usable. Fairly significant power saving can be achieved by defaulting to the integrated graphics when high performance is not required. In total there are 3 display outputs from the integrated graphics and an additional 6 outputs from the Radeon graphics for a total of 9.

By moving from GDDR5 to HBM 2 and going to higher integration by packing everything into a single package, Intel has achieved considerably higher density. Intel reported that around 1900 mm² (~3 in²) board space saving has been achieved which is rather significant for ultra-light and ultra-thin notebooks and tablets where logic board area reduction is important. Additionally, this reduces the BOM for OEMs.